1. Field of the Invention
The present invention relates to a function verification method, and more particularly to a function verification of the function blocks of a semiconductor integrated circuit.
2. Description of the Related Art
Recently it has become common to mount many function blocks on an LSI. When a large-scale LSI is designed, it is standard to design it using a circuit function block (hereafter IP core) previously designed. FIG. 10 is a block diagram depicting the relationship of the test bench 1010 and the test pattern 1020 constructed for the function verification of the IP core 1000. Normally the test bench 1010 comprises an input data generation block 1011 for generating input data to the IP core 1000, an output data check block 1012 for checking the expected value of output data, and a reference model 1013.
The input data generation block 1011 generates input data to the IP core 1000 based on the test pattern 1020. The output data check block 1012 checks whether the output of the IP core 1000 is correct based on the output of the reference model.
FIG. 11 is a diagram depicting an example of the IP core 1000 and the test bench 1010 shown in FIG. 10. The test bench 1010 shown in FIG. 11 is drawn to depict the relationship between the IP core 1000, for implementing the communication interface function in frame units, such as Ethernet®, and the test bench 1010. Just like FIG. 10, the test bench 1010 comprises an input data generation block 1011 to input data to the IP core 1000 of the verification target and the output data check block 1012 for the output data from the IP core 1000, although neither are illustrated in FIG. 11. In FIG. 11, the input data to the IP core 1000 is shown as the frame 1015, and the output data from the IP core 1000 as the frame 1016. This is because Ethernet® is an interface which performs communication in frame units. All data exchanged between the test bench 1010 and the IP core 1000, connected to the test bench 1010, is in frame units. The broken line in FIG. 11 indicates the boundary between the test bench 1010 and the IP core 1000, and the left side of the broken line in FIG. 11 is the test bench 1010 and the right side of the broken line is the IP core 1000.
In FIG. 11, the test bench 1010 sends the frame data 1015 to the IP core 1000 of the verification target. This becomes the input to the IP core 1000. In FIG. 11, the test bench 1010 receives the frame data 1016 from the IP core 1000 of the verification target. This becomes the output from the IP core 1000 of the verification target. To verify the operation of the IP core 1000 the test bench 1010 collates the frame of the output data from the IP core 1000 and the expected value of the output.
If the above mentioned IP core is embedded in the LSI as an already designed function block when the LSI is designed, then the function of the entire LSI must be verified after the IP core is embedded in the LSI. However in most conventional cases, the above mentioned test bench 1010 of the IP core 1000 and the test pattern 1020 cannot be directly used to construct a test bench to verify LSI functions. Even when a function is verified only for the IP core, problems occur at times when using the test bench 1010 and the test pattern 1020. This is because when the IP core 1000 is designed, the test bench 1010 and the test pattern 1020 are designed and developed to verity the functions of the IP core 1000 inside another LSI. In order to construct a verification environment for an entire LSI which is newly designed, it is necessary to either integrate necessary functions, of all functions of the test bench 1010, into the verification environment for the entire LSI, or to construct the test bench from scratch. Such a construction of a test bench, however, increases the development period and the development cost.
The background technology on the verification of functions of an LSI is stated in “Reuse Methodology Manual”, Third Edition, 2002, Kluwer Academic Publishers, ISBN 1-4020-7141-8, pp. 239–263, “NIKKEI MICRODEVICES”, 2003 January Edition, PP. 146–149, “NIKKEI MICRODEVICES”, 2003 February Edition, PP. 133–136, and “NIKKEI MICRODEVICES”, 2003 March Edition, PP. 126–130, for example.
As described above, a conventional IP core has a problem in that the time required for the verification of functions of an IP core increases if an IP core is used.